Can the Cyclone V's FPGA handle a 1 Gigabit long shift register?

I've been studying Verilog for about a week now moving from c/c++,

but was wondering if something like this was possible to create a

shift register that was 1 Gigabit long?

Double checking before sending it over USB Blaster II for the board's very first project.

I updated an example Intel/Altera had posted for a serial in serial out

with a clock and shift enable. Here is the change I made:

module Gigabit_Shift_Register(clk,

shift,

sr_in,

sr_out,

);

input clk, shift;

input sr_in;

output sr_out;

reg [999999999:0] sr;

always@(posedge clk)

begin

if (shift == 1'b1)

begin

sr[999999999:1] <= sr[999999998:0];

sr[0] <= sr_in;

end

end

assign sr_out = sr[999999999];

endmodule