Altera_Forum
Honored Contributor
13 years agoCan someone explain this?
So here is the code of my Verilog program:
module measure(clk, in,out); input clk; input signed [11:0] in; output signed [13:0] out; reg [6:0] n; reg [3:0] cnt; wire signed [13:0] out; reg [13:0] counter; assign out=~counter; initial cnt<=4'b0000; always @(posedge clk) begin if(n[6]==1'b1) begin n=7'b0000000; counter[13:10]<={1'b0,(cnt[2:0])}; cnt<=4'b0000; end if(n[6]==1'b0) begin cnt<=4'b1111; end n<=n+1; end endmodule for this version of the program everything goes as planned and the output is negative(2's complement) but if I substitue n=7'b00000000; with n<=7'b0000000; the output becomes 0, can someone please explain this for me? Thanks in advance