Forum Discussion
Altera_Forum
Honored Contributor
12 years agoPhysically, the global clock networks can be driven by dedicated clock pins, by PLLs or by user logic.
They can not be driven by regular I/O pins. However, since they can be driven by users logic, there's a possible work around. Instead of assigning "signal_I_wish_to_be_global" to pin XX11, use lcell helper_cell (.in(helper_signal) .out(signal_I_with_to_be_global)) and assign "helper_signal" to pin XX11 instead. This will increase the pin to signal delay, but it will allow Quartus to use a global network.