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Altera_Forum
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15 years ago

Can FPGA outputs be read back to Quartus or Matlab?

I've designed a demodulator using HDL. The input data is stored in lpm_rom, mif file generated by matlab. I want to verify the output in matlab too after the design is programmed in FPGA, is there a ...
Altera_Forum's avatar
Altera_Forum
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15 years ago

I don't see a principle difference between acquisition with Signaltap and a user design based on internal memory, neither in terms of available RAM capacity nor data transmission speed, as long you are using the JTAG interface to transmit the data. If you intend to use other interfaces, the user design can be faster, but would also involve more effort.