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Altera_Forum's avatar
Altera_Forum
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15 years ago

Can FPGA outputs be read back to Quartus or Matlab?

I've designed a demodulator using HDL. The input data is stored in lpm_rom, mif file generated by matlab. I want to verify the output in matlab too after the design is programmed in FPGA, is there a ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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You need to write some addtional logic, mainly an address counter, and use a RAM instance with one port enabled for the in system memory editor tool. It's easily done with the MegaWizard. Or use SignalTap and export the data to a file.

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Thanks FvM!

Sorry I am not very clear and have some concern

I know SignalTap will do but it's very slow, and I think it's not suitable if the data need to be triggered becomes large. I want to store the outputs in the RAM then export it for Matlab. Does it make sense to log the output in RAM andread back in Matlab, even if the design is running in FPGA? I haven't used system memory editor before