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Altera_Forum
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9 years ago

Can actual delays be implemented with .sdc constrains?

Hi, Can actual delays be implemented with .sdc constrains? I will try to explain what i want to achieve: Lets say i have PLL with two output clocks "pll_c0" and "pll_c1". "pll_c0" d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

The fitter does not follow exact figures when it closes on timing.

Instead it tries to get a timing pass and stop. At best it targets balanced tSU/tH slack