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Altera_Forum
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9 years ago

Can actual delays be implemented with .sdc constrains?

Hi, Can actual delays be implemented with .sdc constrains? I will try to explain what i want to achieve: Lets say i have PLL with two output clocks "pll_c0" and "pll_c1". "pll_c0" d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

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Thank you all,

Do only output Delay chain settings are affected by .sdc constrains? In Assigment editor for MAX 10 I am seeing that valid values for "Delay from Output Register to Output Pin" are 0 and 1. So there is only two options to play with. Does this mean that no matter what you do with your constrains you can not get more or less delay except only those two valid settings for Delay chain?

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I presume the fitter will have more options internally for routing delays between io register and its buffer. The setting of 0/1 is just an extra for user.