Can actual delays be implemented with .sdc constrains?

I think it is better to describe set_output_delay as defined by Synopsis.

min is the delay required from the latch edge and max is the delay required to the latch edge. Thus min equates with -tH of external device while max equates with +tSU

of external device (assuming board level data delay = clock delay). Thus if we want early/late margin of data transition window then:

early margin = negative of min delay figure

late margin = clock period – max delay

if both are zero we get early margin = 0 and late margin = clock period i.e. data can change anytime, in effect no requirement

The delay figures given are just information and are then translated by fitter to whatever delays required within fpga.