Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

Can actual delays be implemented with .sdc constrains?

Hi, Can actual delays be implemented with .sdc constrains? I will try to explain what i want to achieve: Lets say i have PLL with two output clocks "pll_c0" and "pll_c1". "pll_c0" d...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
9 years ago

--- Quote Start ---

What device?

--- Quote End ---

Cyclone IV, or MAX 10.

--- Quote Start ---

The PLL won't phase-shift an output due to constraints, that has to be done manually

--- Quote End ---

Yes, ofcourse I understand that and I use for this purpose dynamic phase shift option. :)

Can you explain how set_output_delay command in .sdc file relates to Delay Chain values? I have tried to set Delay chain values manualy but for now i can not understand how to set my .sdc file?