Honored Contributor
Honored ContributorWhat device?
The PLL won't phase-shift an output due to constraints, that has to be done manually. The PLL also drives a global clock tree to get to the dataout DDR, so there is no way for it to change that delay. What the fitter can do is modify the output delay chains in the IO cell to meet the timing requirements, which should work(and I have seen work many times). Go to the Fitter Report -> Delay Chain Summary and see what's going on. It might be that it's pegged to the highest or lowest delay chain value and therefore can't move them anymore. I've also seen cases where I'm only looking at one timing model and thinking it should do something else, but if I look across all timing models it turns out it's doing the right thing. (I've also seen a case where there was a bug and it just chose the wrong value. If you want, you can manually assign the delay chain values in the Assignment Editor)
