buswidth change after place & route

Dear All,

We are on the edge of doing post place& route netlist simulations on our design which will be mapped onto a cycloneiii device.

Functional simulations go fine with modelsim.

The netlist writer generated a .vho and sdo file for us.

However modelsim is not able to work with this netlist file cause

Quartus changed all buswidths from and to all instantiated (lpm) memories.

On the generic map (in the netlist) they all seem fine (either 36 or 18).

The busses to the instantiation are all changed to 144-bit.

The signals defined , connecting them up, are all 144-bit and the remaining bits (143 downto 36) are all gnd. So we have a clear buswidth mismath between signal and port width.

The work around is to change all signals by hand. Since there are a lot of them it takes a long time.

Another work around is to make all fifo's 144-bit width.

This does not work. Modelsim will terminate with a memory allocation error.

What went wrong during place and route ?

grtz

Simon