New Contributor
Yeah, I'd just convert to HDL and use that if you have more complex designs causing this issue. Just save yourself the time and effort trying to fix the schematics.
Super ContributorBecause this was driving me crazy, I finally downloaded your design and opened it in Standard so I could generate an HDL file from the .bdf (a feature that for some reason is not available in Pro). I think the issue is that VCC above the register is connected to the preset and reset inputs of the register. If you have both preset and clear pulled up to Vcc, synthesis has to account for both control inputs. Obviously, there is no way for either input to go low, but synthesis is trying to account for that possibility so the tool synthesizes an 8-bit bus wire and sets its value to 1 (instead of 0xff strangely). This bus wire also is little endian instead of big endian and this explains the strangeness you are seeing. Normally you would just leave these inputs unconnected if you were not using them.
I'm not sure if this is a bug or what, but I'm attaching the HDL code from your schematic and also the code when I disconnected VCC from the PRN input but left it connected to the CLRN input, which is almost as strange.
New ContributorSorry to drag you into this insanity as well : -)
Hmm. That little-endian vector sure may be a clue to what's going on. Also interesting with the generated RTL that you posted is that y_out is assigned x_in inputs in the correct order there: y_out[7] <= x_in[7].
I disconnected the CLRN and PRN signals from the flip-flop:
The synthesized result still has connections reversed:
Also, the schematic from my actual design has a number of inputs and outputs that aren't being fed to simple registers and those connections are reversed, too.
I appreciate your taking a look at this!
Paul
