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pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
5 years ago
Solved

Bus index reversal when SystemVerilog module instantiates a BDF in Quartus Prime Pro 21.2

I have a legacy BDF that I need to use in a current design. Using Quartus Prime Pro v20.4 or v21.2, I see the bus indexes reversed on the port connections when the BDF diagram is instantiated from wi...
  • sstrell's avatar
    sstrell
    5 years ago

    Yeah, I'd just convert to HDL and use that if you have more complex designs causing this issue. Just save yourself the time and effort trying to fix the schematics.

sstrell's avatar
sstrell
Icon for Super Contributor rankSuper Contributor
5 years ago

Weird. Have you tried explicitly specifying [3:0] in the instantiation or creating a wire to perform the concatenation outside of the instantiation?

pnp's avatar
pnp
Icon for New Contributor rankNew Contributor
5 years ago

Thanks! Yes, I tried all of those combinations that you suggested. Using a wire and concatenating results in the same reversed connections:

module top
(
   input logic clk,
   input logic [3:0] x,
   output logic [7:0] y
);

wire [7:0] x_in;
assign x_in = {x, 4'b0};

bdftest bdf_i
(
   .clk(clk),
   .x_in(x_in),
   .y_out(y)
);

endmodule

As does using a register:

module top
(
   input logic clk,
   input logic [3:0] x,
   output logic [7:0] y
);

logic [7:0] x_in;
always @(posedge clk)
   x_in <= {x, 4'b0};

bdftest bdf_i
(
   .clk(clk),
   .x_in(x_in),
   .y_out(y)
);
endmodule

As well as a register with explicit indexes in the assignment and instantiation:

module top
(
   input logic clk,
   input logic [3:0] x,
   output logic [7:0] y
);
logic [7:0] x_in;
always @(posedge clk)
begin
   x_in[7:4] <= x;
   x_in[3:0] <= 4'b0;
end

bdftest bdf_i
(
   .clk(clk),
   .x_in(x_in[7:0]),
   .y_out(y)
);
endmodule

And finally, same results with a wire and explicit assignment/instantiation:

module top
(
   input logic clk,
   input logic [3:0] x,
   output logic [7:0] y
);

wire [7:0] x_in;
assign x_in[7:4] = x;
assign x_in[3:0] = 4'b0;

bdftest bdf_i
(
   .clk(clk),
   .x_in(x_in[7:0]),
   .y_out(y)
);
endmodule