New Contributor
Yeah, I'd just convert to HDL and use that if you have more complex designs causing this issue. Just save yourself the time and effort trying to fix the schematics.
Super ContributorWeird. Have you tried explicitly specifying [3:0] in the instantiation or creating a wire to perform the concatenation outside of the instantiation?
New ContributorThanks! Yes, I tried all of those combinations that you suggested. Using a wire and concatenating results in the same reversed connections:
module top ( input logic clk, input logic [3:0] x, output logic [7:0] y ); wire [7:0] x_in; assign x_in = {x, 4'b0}; bdftest bdf_i ( .clk(clk), .x_in(x_in), .y_out(y) ); endmodule
As does using a register:
module top ( input logic clk, input logic [3:0] x, output logic [7:0] y ); logic [7:0] x_in; always @(posedge clk) x_in <= {x, 4'b0}; bdftest bdf_i ( .clk(clk), .x_in(x_in), .y_out(y) ); endmodule
As well as a register with explicit indexes in the assignment and instantiation:
module top ( input logic clk, input logic [3:0] x, output logic [7:0] y ); logic [7:0] x_in; always @(posedge clk) begin x_in[7:4] <= x; x_in[3:0] <= 4'b0; end bdftest bdf_i ( .clk(clk), .x_in(x_in[7:0]), .y_out(y) ); endmodule
And finally, same results with a wire and explicit assignment/instantiation:
module top ( input logic clk, input logic [3:0] x, output logic [7:0] y ); wire [7:0] x_in; assign x_in[7:4] = x; assign x_in[3:0] = 4'b0; bdftest bdf_i ( .clk(clk), .x_in(x_in[7:0]), .y_out(y) ); endmodule
