Building an SPI Decoder into Altera

You're using an asynchronous signal as a clock, bad idea.

If you want to use SPI select deasserting to indicate when to load a parallel output register, then you can use exactly the same edge-detection technique to generate a pulse when SPI_sel deasserts. You need to have a dual-DFF synchronizer, followed by your edge-detect logic.

Change the process to use your FPGA clock, and use the spi_sel_rising_edge pulse to enable your parallel output registers at the end of each SPI transaction.

Cheers,

Dave