Building an SPI Decoder into Altera

Hi Dave, thanks for your help!!

I added edge detection logic, routing the SPI_Clk signal into a D-FF and using Q' ANDed with SPI_Clk as my spi_rising_edge. I believe this logic works well. Then, I loaded data into shift_reg64 as you suggested, using spi_rising_edge as an enable. So all this should work fine, right? I think I'm still losing some info on my data though.

Could it be the way I'm reading from the register to define the outputs?

process (SPI_Sel) begin
	if rising_edge(SPI_Sel) then
		outA <= "000" & shift_reg64(60 downto 32);
		outB <= "000" & shift_reg64(28 downto 0);
		SEL_h <= shift_reg64(63 downto 61);--"000";
		SEL_l <= shift_reg64(31 downto 29);--"000";
	end if;
end process;

Is there an error in this or does it look fine?

Thanks!

Gabriel