Building an SPI Decoder into Altera

You're getting close;

1. Add logic to detect the rising-edge of SPI clock

Hint: you can create a single clk period pulse by routing the synchronized spi_clk output through a register, and then using a gate, eg., or, and, xor, with the synchronized and delayed synchronized signal. Call this spi_clk_rising ('cause later you may need an spi_clk_falling version :) )

2. Use the rising-edge pulse as an enable to your shift-register, i.e., in the code above, use

process (Clk, Reset) begin
    if Reset = '1' then
        shift_reg64 <= (others => '0');
    elsif rising_edge(Clk) then
                if (spi_rising_edge = '1') then
              shift_reg64(63 downto 0) <= shift_reg64(62 downto 0) & SPI_Data;
                end if;
    end if;
end process;

Cheers,

Dave