Building an SPI Decoder into Altera

Ok, this is my newest status. I built a state machine to make the SPI_Clk into a regular signal and this is what I came up with:

process (Clk, Reset) begin
	if Reset = '1' then
		shift_reg64 <= x"0000000000000000";
	elsif rising_edge(Clk) and SPI_Clk = '1' then
		shift_reg64(63 downto 0) <= shift_reg64(62 downto 0) & SPI_Data;
	end if;
end process;
process (SPI_Sel) begin
	if rising_edge(SPI_Sel) then
		outA <= "000" & shift_reg64(60 downto 32);
		outB <= "000" & shift_reg64(28 downto 0);
		SEL_h <= shift_reg64(63 downto 61);--"000";
		SEL_l <= shift_reg64(31 downto 29);--"000";
	end if;
end process;

This looks pretty much the same, but in my top-level .bdf I'm running the SPI clock straight from GPIO through two D-FFs in series which are clocked with the 50MHz clock. The output of the second D-FF goes into the SPI decoder from the code above as SPI_Clk. I believe now this should be working right, but somehow it still isn't!! If anyone can see where I went wrong, I'd deeply appreciate it! Thanks!!