Forum Discussion
Altera_Forum
Honored Contributor
12 years agoThe sensitivity lists are fairly meaningless for synthesis - they are ignored. The logic is taken just from whats inside the process.
Using the system clock is just fine. If you read the SPI spec you'll see it has some leeway on timing. It is much better to use the single system clock and treat the SPI_clk as just another signal. Detect the rising edge of it and then you know where the data is.