Building an SPI Decoder into Altera

Hi,

BadOmen: Thanks for your suggestions and for moving the thread to a correct subforum. Sorry for posting into the wrong one.

k0007 and Tricky: I understand what you're saying, but I have a few questions! Thanks for your help. First, isn't the SPI clock synced with the serial data in order to have a stable output at every clock sample? If I use my internal FPGA clock, which is about 20x faster, I believe, wouldn't I be oversampling and get corrupted data. Or what do you mean by resampling? Store the SPI info on a tmp register and then load it into a new register which is loaded at every FPGA clock cycle? Also, by creating two clock domains you mean the fact that I'm using two if-else statements? But the SPI_Sel acts just as an enable, so I don't see how this could cause a problem. Finally, regarding the sensitivity list,the compiler throws warnings if other values I'm reading (ie _Data, _Sel, shift_reg64) are not in the sensitivity list. I'm not 100% sure what it represents exactly... If you could clarify this, I'd very much appreciate it!

Thanks for your help, and I'm sorry I rambled a bit there.

Gabriel