Forum Discussion
Altera_Forum
Honored Contributor
12 years agonormally the process list should only contains the clock (or an asynchrounous reset) so you could try by changing
process (SPI_Clk, SPI_Data, SPI_Sel, shift_reg64) begin into process (SPI_Clk) and process (SPI_Sel, shift_reg64) into process (SPI_Sel) but I still wouldn't recommend this because you create two clock domains by doing this (SPI_SEL & SPI_Clk). I think it's much better if you process everything on some clock present in your FPGA (maybe the clock you use to read the outA , outB, ... with ? )