Forum Discussion
Altera_Forum
Honored Contributor
12 years agoMoving to the VHDL coding subforum. Unfortunately my VHDL is too rusty for me to offer a suggestion on what might be happening.
Some observations/suggestions: - I recommend implementing reset conditions for your registers - If your data that is being transferred from one clock domain to the SPI clock domain you should probably refactor your code to operate on the data clock domain (which I assume is faster) and use the SPI clock as a shift enable