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EGrub's avatar
EGrub
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

BUG in simulation library for dcfifo_mixed_widths with Modelsim

If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails. With the read request signal the output changes immedia...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago

Hi,

Can you add the delay for rdreq with respect to the posedge of the rdclk and see if the problem persists?

Thanks.