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EGrub's avatar
EGrub
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

BUG in simulation library for dcfifo_mixed_widths with Modelsim

If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails. With the read request signal the output changes immedia...
KhaiChein_Y_Intel's avatar
KhaiChein_Y_Intel
Icon for Regular Contributor rankRegular Contributor
6 years ago
Hi, May I know how do you write the testbench for the two scenarios described above? - No signal or just the request signals are delayed with 23ps - All the signals (including clock) are delayed by the same amount of time (23ps) Thanks.