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EGrub
Occasional Contributor
Occasional ContributorBUG in simulation library for dcfifo_mixed_widths with Modelsim
If a dcfifo_mixed_widths is used (because I need the mixed width) but write and read side getting the same clock signal then simulation fails. With the read request signal the output changes immedia...
EGrubOccasional Contributor
Occasional ContributorHi Khai Chein!
Your simulation seems to work, I had issues when I delayed all signals by 23ps.
I know that is not the usual case and it was not my intention to do so.
Best regards,
Erich
