Blocking/Nonblocking assignments in SystemVerilog always block

LRM says: The always_ff procedure imposes the restriction that it contains one and only one event control and no blocking timing controls. Variables on the left-hand side of assignments within an always_ff procedure, including variables from the contents of a called function, shall not be written to by any other process.

Software tools should perform additional checks to warn if the behavior within an always_ff procedure does not represent sequential logic.

A blocking assignment is not a blocking timing control. Blocking timing controls are# , @, wait, and task calls. Thus,

always_ff @(posedge clk) begin // LEGAL

logic temp;

temp=a && b; // local evaluation, for later usage

if(temp) c <= d;

end

always_ff @(posedge clk) begin // ILLEGAL

logic temp;

# 1 // <<<< ILLEGAL

temp=a && b; // local evaluation, for later usage

if(temp) e <= d;

end

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Ben Cohen (831) 345-1759

http://www.systemverilog.us/ ben@systemverilog.us

* SystemVerilog Assertions Handbook, 2nd Edition, 2010 ISBN 878-0-9705394-8-7

* A Pragmatic Approach to VMM Adoption 2006 ISBN 0-9705394-9-5

* Using PSL/SUGAR for Formal and Dynamic Verification 2nd Edition, 2004, ISBN 0-9705394-6-0

* Real Chip Design and Verification Using Verilog and VHDL, 2002 isbn 0-9705394-2-8

* Component Design by Example, 2001 ISBN 0-9705394-0-1

* VHDL Coding Styles and Methodologies, 2nd Edition, 1999 ISBN 0-7923-8474-1

* VHDL Answers to Frequently Asked Questions, 2nd Edition ISBN 0-7923-8115

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