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DNguy4
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

blackbox file

Hi, I have a VHDL blackbox file my_file_bb.vhd in which I declare all the input and output ports. When I instantiate it from another program ... entity TEST: my_file port map.... Quartus keeps co...
DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

It's working now. I forgot to declare it as a component.

Thanks