Forum Discussion

DNguy4's avatar
DNguy4
Icon for Occasional Contributor rankOccasional Contributor
6 years ago

blackbox file

Hi, I have a VHDL blackbox file my_file_bb.vhd in which I declare all the input and output ports. When I instantiate it from another program ... entity TEST: my_file port map.... Quartus keeps co...
Abe's avatar
Abe
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

The issue here is you've used the VHDL black box module without declaring it. Before you use the BB module in your VHDL Architecture block via a Port Map, you have to declare the BB module as a Component. All you need to do is to add a component declaration for the black box module under the Architecture block and then use it in the Port Map.

Architecture RTL of XXX Is

Component my_file Is

Port (

.....

.....

);

end component;

Begin

Port Map ( );

It should resolve the issue. Else post back with your code and we'll help you resolve it.