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Altera_Forum's avatar
Altera_Forum
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12 years ago

Bit error tester to test FPGA

the PRBS generates bits using 4 bit LFSR. i want to test for the bit error at the receiver using VHDL code. Using FIFO would be a good option to store the bits one by one? And the same LFSR ca...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

I am facing similar problem.

I am using an optical fiber to transmit the data. So there will be delay. Can you write the part of the code that will do the waiting for data and enabling checking?