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Altera_Forum
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12 years ago

Bit error tester to test FPGA

the PRBS generates bits using 4 bit LFSR. i want to test for the bit error at the receiver using VHDL code. Using FIFO would be a good option to store the bits one by one? And the same LFSR ca...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

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I am kind of confused as to how to enable the output of prbs to be in sink with the incoming received bits to make the comparison to check for bit error.

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if you have real tx/rx system in action then you expect some delay for data to reach rx from tx.

Thus the rx must generate a data valid signal to indicate validity of data. You wait for this valid to appear and use as enable for your prbs.