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Altera_Forum
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12 years ago

Bit error tester to test FPGA

the PRBS generates bits using 4 bit LFSR. i want to test for the bit error at the receiver using VHDL code. Using FIFO would be a good option to store the bits one by one? And the same LFSR ca...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

OK, you don't really need to save input bits. Instead put enable on your prbs(by the way that loop on prbs is not needed). you check when your input arrives and enable prbs first output with first input then prbs will run hand in hand with input bits per clock cycle.