--
entity ber is
port ( rxd_bit : in std_logic;
clk : in std_logic);
end ber;
I suggest using some output flag. Moreover use numeric_std rather other libraries for type conversion
architecture ar of ber is
type data is array(0 to 63) of std_logic;
signal d: data;
signal c,m,t: integer:=0;
signal count: integer:=0;
signal q:bit_vector(3 downto 0):="0001";
signal k:bit_vector(3 downto 0);
you don't need to declare c,t as they are loop indices
m is doing nothing
use std_logic and std_logic_vector. No need to mix with bit_vector.
begin
process(clk) is
begin
for c in 0 to 63 loop
if rising_edge(clk) then
d(c)<= rxd_bit;
end if;
end loop;
this is not saving 64 input samples but just repeating one sample 64 times into 64 bits
for xor I will write if (a xor b) = '1' then
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