Bit error tester to test FPGA

i have attached the vhdl code for the reciever. I have generated the same pseudo random sequence as that of the txr, in the rxr also and compared each bit with the received data. If the value is different , count is incremented.

I am constantly getting the following error:

1. No feasible entries for infix operator "xor".

2. Type error resolving infix expression "xor" as type std.standard.boolean.

library ieee;

use ieee.std_logic_1164.all;

use ieee.std_logic_unsigned.all;

use ieee.numeric_std.all;

use ieee.std_logic_arith.all;

use ieee.std_logic_textio.all;

--

entity ber is

port ( rxd_bit : in std_logic;

clk : in std_logic);

end ber;

architecture ar of ber is

type data is array(0 to 63) of std_logic;

signal d: data;

signal c,m,t: integer:=0;

signal count: integer:=0;

signal q:bit_vector(3 downto 0):="0001";

signal k:bit_vector(3 downto 0);

begin

process(clk) is

begin

for c in 0 to 63 loop

if rising_edge(clk) then

d(c)<= rxd_bit;

end if;

end loop;

for i in 0 to 15 loop

q<=(q(2)xor q(3)) &q(0)&q(1)&q(2);

k<=q;

for t in 0 to 3 loop

if(k(t) xor d(t)) then ---------------------> error in this line

count<= count+1;

m<= m+1;

end if;

end loop;

end loop;

end process;

end ar;