Bit error tester to test FPGA

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the PRBS generates bits using 4 bit LFSR. i want to test for the bit error at the receiver using VHDL code. Using FIFO would be a good option to store the bits one by one?

And the same LFSR can be used at the receiver to compare it with the received bits right?

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right. But you don't need fifo to store. Just generate tx prbs, send it as it generates. At receiver use an instant of same prbs with same seed but activate it when rx data arrives (after some delay).