birectional port

for the simulation the output data correctly appears on the BIDIR[x]~result lines but it doesn't appear on the regular BIDIR[x] lines. is this normal? is there a way to combine the 8 BIDIR[x]~result lines so that they appear as one bus line instead of 8 single lines ?

http://img267.imageshack.us/img267/8416/bidirbs1.png

library ieee;
use ieee.std_logic_1164.all;
entity bidirection is
port (
      E     : in std_logic;
      BIDIR    : inout std_logic_vector(7 downto 0)
      );
end bidirection;
architecture behaviour of bidirection is
signal A : std_logic_vector(7 downto 0) := "11110000";
begin
process(E)
begin
if(E = '0') then
	BIDIR <= A;
else
	BIDIR <= "ZZZZZZZZ";
end if;
end process;
end behaviour;