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Altera_Forum
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17 years ago

Best way to store ethernet frames?

For a class project I need a way to store ethernet frames in SRAM on an fpga. My first goal would be to be able to recognize when an ethernet frame is being sent. I can do that based on the preamble because I know that the preamble is an alternating pattern of 0's and 1's ending in 11. I was thinking of storing this in a shift register which would output to a std_logic_vector signal which I could check to make sure it was correct. But that's a 64 bit vector. Do you think that that is a good idea?

Thanks

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Here's something I'm trying to write to begin: 

    
library ieee;
use ieee.std_logic_1164.all;
entity FrameHolder is
	port
	(
		clk,reset: in std_logic;
		input: in std_logic;
		foundframestart : out std_logic;
		output: out std_logic
	);
end FrameHolder;
architecture structure of FrameHolder is
	signal prehold: std_logic_vector(63 downto 0);
	
	signal frame: std_logic;
	signal counter: integer range 0 to 1510;
	
	
	component preamble
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
	);
	end component;
	
begin
	process(clk,reset,input,frame)
	begin
		if(reset = '1') then
			counter<=0;
		elsif(clk'event and clk='1' and frame <= '1') then
			counter<=counter+1;
		end if;
	end process;
	
	pre: preamble port map(reset,clk,not frame,input,prehold);
	
foundframestart <= '1' when prehold = "1101010101010101010101010101010101010101010101010101010101010101" and counter = 0 else '0';
frame <= '1' when prehold = "1101010101010101010101010101010101010101010101010101010101010101" and counter = 0 else '0';
end structure;

    For now, foundframestart and frame are the same thing. I want to know when I've found an ethernet frame and then start counting the next bits after finding the ethernet frame. However, VHDL is getting rid of my signal and thus taking it out of the elsif statement and counter is always being incremented and my output never goes high.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    17 years ago

    Slight change, the counter still starts too early (it starts right away) because the frame signal is being synthesized away or something. 

    
library ieee;
use ieee.std_logic_1164.all;
entity FrameHolder is
	port
	(
		clk,reset: in std_logic;
		input: in std_logic;
		foundframestart : out std_logic;
		countout: out integer range 0 to 1510;
		output: out std_logic
	);
end FrameHolder;
architecture structure of FrameHolder is
	signal prehold: std_logic_vector(63 downto 0);
	
	signal frame: std_logic;
	signal counter: integer range 0 to 1510;
	
	
	component preamble
	PORT
	(
		aclr		: IN STD_LOGIC ;
		clock		: IN STD_LOGIC ;
		enable		: IN STD_LOGIC ;
		shiftin		: IN STD_LOGIC ;
		q		: OUT STD_LOGIC_VECTOR (63 DOWNTO 0)
	);
	end component;
	
begin
	process(clk,reset,input)
	begin
		if(reset = '1') then
			counter<=0;
		elsif(clk'event and clk='1' and frame <= '1') then
			counter<=counter+1;
		end if;
	end process;
	
	pre: preamble port map(reset,clk,not frame,input,prehold);
	
frame <= '1' when prehold = "1101010101010101010101010101010101010101010101010101010101010101" else '0';
foundframestart <= frame;
countout <= counter;