--- Quote Start ---
I thought that wait request is used to tell the master port that it needs to wait for the data for more then 1 clock cycle.
--- Quote End ---
The waitrequest signal is low to indicate that a transaction has been accepted, and high to insert wait-states.
In the example I have just show, waitrequest is always low, since the registers component can accept a read or write on every clock. The read data has a single-clock pipeline delay, so readdatavalid asserts along with the read data on the clock after the transaction has been accepted.
If you create a Avalon Verification IP suite design containing your slave component, you can test this.
Cheers,
Dave
Honored Contributor
