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Altera_Forum
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13 years ago

Best way to interface my CPU

Hello, I am wondering what is the best way to interface my 32-bit RISC CPU. I need to interface it with the sdram memory, the flash memory, and possibly the sram memory. I will also need to dedicate ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

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Won't it be fine if I do all the code in VHDL except for the interface to QSYS. I will just make my VHDL code a component and put it in Verilog

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Mixing source is fine if you have modelsim-se as it supports mixed-language simulation.

modelsim-ase only supports single-language simulation.

You cannot use the synthesis and create .vo netlist trick, since the BFM cannot be synthesized.

Cheers,

Dave