Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Best way to interface my CPU

Hello, I am wondering what is the best way to interface my 32-bit RISC CPU. I need to interface it with the sdram memory, the flash memory, and possibly the sram memory. I will also need to dedicate ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

Can I just export the QSYS system as a bsf file, place it in the upper entity bdf file and then run it on as such or do I actually have to run it a specific way.

Sigh... Guess like I need to teach myself verilog then.

EDIT: Won't it be fine if I do all the code in VHDL except for the interface to QSYS. I will just make my VHDL code a component and put it in Verilog