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Now I am confused on how the BFM is going to work. It seems like there is no way how to interface it with a testbench.
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A testbench contains a Qsys system and the BFM is a component in that system.
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Also I would prefer to do the coding in VHDL and I cant find any VHDL for it.
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Altera doesn't support VHDL particularly well in Qsys ...
Do you have access to Modelsim-SE? If so, you can use mixed language simulation. If you are using Modelsim-ASE, then you can probably use Quartus to synthesize to a .vo netlist and simulate that. In that case, you'd have to create the _hw.tcl component to point at the .vo file, not your VHDL file. I haven't needed to try this route, so perhaps others on the forum can provide their recommendations.
Cheers,
Dave
Honored Contributor
