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I would be glad to here your suggestion, I know adding inverters is goofy.
Yes the clock driving the logic is 2x the output clock speed. We need to keep minimum latency .
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Hi jstander,
maybe this could work:
1. Resample the clock divided by 2 with a register clock by the higher clock. Add to your data signal(s) also an register and place all FF in the I/O cells of the FPGA. By inverting the divided clock you should always have 1/2 clock period between the active clock edge and your data change. The only problem I could see is whether you got always the same clock phase on the resampled clock?:confused:
Honored Contributor
