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Altera_Forum's avatar
Altera_Forum
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17 years ago

Best way to force extra pad delay?

Hi, I am using TimeQuest, I have two signals CLK and CS_L both driven off the same clock that go to ports on the chip. I have them constrained to force CS_L to be delayed 1.5 nsec from CLK. TimeQu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I would be glad to here your suggestion, I know adding inverters is goofy.

Yes the clock driving the logic is 2x the output clock speed. We need to keep minimum latency .