Best way to code a clock divider?

There are some errors in that code (inconsistent port names). Here is a corrected version:

LIBRARY IEEE;
USE  IEEE.STD_LOGIC_1164.all;
USE  IEEE.STD_LOGIC_ARITH.all;
USE  IEEE.STD_LOGIC_UNSIGNED.all;
entity divider is
	port (CLKIN  : in  std_logic;  
               RESET  : in  std_logic;  
	       CLKOUT : out std_logic );
end entity divider; 
architecture divider_2048 of divider is
	signal cnt : unsigned(10 downto 0);
	begin  
		process(RESET, CLKIN)  
		begin
			if RESET = '1' then  
				cnt <= (others => '0');
			elsif rising_edge(CLKIN) then  
				cnt <= cnt + 1;   
			end if;  
		end process;   
		CLKOUT <= cnt(10); 
end architecture divider_2048;