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Altera_Forum
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13 years ago

Best way to code a clock divider?

Hello, I have to divide a clock input signal by 2048. I was wondering which method was the best to implement this divider in a FPGA. I know that we can use either a counter or just some flip-fl...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

What's the reason of manually synthesizing a counter, like you did? The logic synthesizer is supposed to do that boring job.

In VHDL you can simply increment a 11bit count register and take the MSB.

For example: 


entity divider is
	port (CLKIN  : in  std_logic;  
               RESET  : in  std_logic;  
	       CLKOUT : out std_logic );
end entity divider; 
architecture divider_2048 of divider is
	signal cnt : unsigned(10 downto 0);
	begin  
		process(RESET, CLK)  
		begin
			if RESET = '1' then  
				cnt <= (others => '0');
			elsif rising_edge(CLK) then  
				cnt <= cnt + 1;   
			end if;  
		end process;   
		Q <= cnt(10); 
end architecture divider_2048;