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Altera_Forum
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13 years ago

Best way to code a clock divider?

Hello, I have to divide a clock input signal by 2048. I was wondering which method was the best to implement this divider in a FPGA. I know that we can use either a counter or just some flip-fl...
Altera_Forum's avatar
Altera_Forum
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13 years ago

well I certainly wouldnt do it like that.

The best way is to create a clock enable rather than an actual clock (so you clock the slow thing at the system clock rate, and only enable it once every 2048 clocks). Creating clocks from logic can create timing issues.