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Altera_Forum
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14 years ago

[B]ERROR:object "std_logic_signed" is used but not declared[/B]

hi there, I'm VHDL beginner working on a Filter code, which is shown below and i'm getting the error as "error (10482): vhdl error at fir.vhd(17): object "std_logic_signed" is used but not declar...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Try this: 


library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
 entity fir is 
  
   port(clk : in std_logic;
         rst : in std_logic;
         din : in signed(7 downto 0);
         dout : out signed(18 downto 0));
        end entity;

Cheers,

Dave