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Altera_Forum
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11 years ago

[beginner] D Latch issue

Hi I am new to VHDL programming and I seem to have an issue simulating a D Latch in Quartus II. The main issue is that my code seems to keep transferring input D to output Q when enable E is low(0), ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

Are you sure you want to build a transparant latch? it will be prone to timing issues, which you are probably seeing in the waveform (as the quartus simulator only simulates gate level designs). FPGAs are designed for clocked flip-flops.

Have you got a testbench for this code? have you tried modelsim instead?