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Altera_Forum's avatar
Altera_Forum
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11 years ago

Begginer needs help on clock counter

Like I said I am a beginner to the VHDL language and the clock prototype that I am trying to build. My problem is that my clock goes from 00:58:00 to 01:59:00 to 02:00:00....The seconds works fine but the mins and hours is not matching up correctly. I am begging someone to please help me to show me whats wrong or to lead me in the right direction

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    I haven't checked the code yet, but on Clock_Integration.bdf the "fig10_29" clock source is the "tc" signal from "Mod_60_Integration" and the "ena" source is the "clk". Was this intended? It looks like they are mismatched.

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    @tcnasc yes it was intended because it gave me two different outcomes. It either switches by 7 or it does that little second thing as earlier described