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Altera_Forum's avatar
Altera_Forum
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8 years ago

Basic question about Signals

Hi, I'm beginner in VHDL; My Question is ; when we define a signal as std_logic, but without any value. Is it same of saying that signal's starting value is '0' ?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

thank you so much, it's done.