Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Basic question about Signals

Hi, I'm beginner in VHDL; My Question is ; when we define a signal as std_logic, but without any value. Is it same of saying that signal's starting value is '0' ?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Thank you, Do I mind you to read my last post?