Basic question about Signals

Thank you for your consideration, I got it and initialized all signals. On testbench wave, I was seeing 'U' at out. now it's fixed. But, At that time my CLK_50Mhz input defined in Entity started to be seen 'U' . Do I have to initialize 'CLK_50Mhz' in entity port as well? Please take a look on my basic code.

entity son is port

(

CLK_50MHz: in std_logic;

myLED: out std_logic

);

end son;

architecture behavior of son is

signal counter:std_logic_vector(24 downto 0):="0000000000000000000000000";

signal CLK_1Hz:std_logic :='0';

begin

--1011111010111100001000000

prescaler: process(CLK_50MHz)

begin

if rising_edge(CLK_50MHz) then

if counter<"1011111010111100001000000" then

counter<=counter+1;

else

CLK_1Hz <= not CLK_1Hz;

counter <= (others => '0');

end if;

end if;

end process prescaler;

myLED<=CLK_1Hz;

end behavior;

That's a basic led blink, On testbench wave, getting CLK_50Mhz = 'U' and myLED = 0.

and this's my testbench code( I don't post libraries here to keep the code short.)

ENTITY testbench2 IS

END ;

ARCHITECTURE testbench2_arch OF testbench2 IS

SIGNAL CLK_50MHz : STD_LOGIC ;

SIGNAL myLED : STD_LOGIC ;

COMPONENT son

PORT (

CLK_50MHz : in STD_LOGIC ;

myLED : out STD_LOGIC );

END COMPONENT ;

BEGIN

DUT : son

PORT MAP (

CLK_50MHz => CLK_50MHz ,

myLED => myLED ) ;

-- "Clock Pattern" : dutyCycle = 50

-- Start Time = 0 ps, End Time = 1 ns, Period = 100 ps

clk_50mhz <= not clk_50mhz after 20 ns /2 ;

-- "Constant Pattern"

-- Start Time = 0 ps, End Time = 1 ns, Period = 0 ps

Process

Begin

if myled /= ('0' ) then

report " test case failed" severity error; end if;

wait for 1 ns ;

-- dumped values till 1 ns

wait;

End Process;

END;

THANKS AND BEST REGARDS